The present invention relates generally to non-volatile memories and in particular the present invention relates to precharging data lines in a non-volatile memory device.
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a periodic refresh of electricity to maintain its contents. Computers often contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into erasable blocks. Each of the memory cells can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
In one method of programming a memory cell, a high positive voltage Vg is applied to the gate of the cell. In addition, a moderate positive voltage is applied to the drain (Vd) and the source voltage (Vs) and the substrate voltage (Vsub) are at ground level. These conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the gate and collect on the floating gate. The electrons remain on the floating gate and function to reduce the effective threshold voltage of the cell as compared to a cell that has not been programmed. A programmed non-volatile memory cell is said to be at a logic level of xe2x80x9c0xe2x80x9d. In Flash memories, blocks of memory cells are erased in groups. This is achieved by putting a negative voltage on the word lines of an entire block and coupling the source connection of the entire block to Vcc (power supply), or higher. This creates a field that removes electrons from the floating gates of the memory elements. In an erased state, the memory cells can be activated using a lower gate voltage. An erased non-volatile memory cell is said to be at a logic level of xe2x80x9c1xe2x80x9d.
Non-volatile memory systems, including Flash memory systems, use a variety of sense amplifiers to verify the state of memory cells in a memory array. One method of verifying a non-volatile memory cell is accomplished by applying a potential to the gate of the cell to be verified and then using a sense amplifier to compare a current generated by the cell with a known current from a reference cell. The reference cell is a non-volatile memory cell or bit that has a predefined charge that is set or trimmed by the manufacture of the memory to produce a specific reference current. The sense amplifier determines whether the memory cell to be verified draws more or less current than the reference current. By doing this, the sense amplifier determines if the memory cell is in a programmed state or an erased state.
Before a read or verify operation is performed by a sense amplifier, global data lines that couple the memory array to the sense amplifier are often precharged to a predetermined value. The time needed to precharge the global data lines reduces the overall speed of the sense amplifier. This time limitation becomes crucial as Flash memory devices are designed to perform operations in faster and faster times.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method of precharging data lines.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a Flash memory sense amplifier precharge device is disclosed. The Flash memory sense amplifier precharge device comprises a self-bias circuit and a precharge circuit. The self-bias circuit is coupled to precharge a data node in response to a first control signal. The precharge circuit is coupled to precharge the data node in response to a second control signal, wherein the second control signal is different from the first control signal.
In another embodiment, a current sense amplifier precharge device for a non-volatile memory comprises a self-bias circuit and a precharge circuit. The self-bias circuit is coupled to precharge a data node. The precharge circuit is coupled to precharge the data node, wherein the precharge circuit supplies a current pulse to the data node to precharge the data node faster than the self-bias circuit could by itself.
In another embodiment, a current sense amplifier comprises a first self-biasing circuit, a first precharge circuit, a second self-bias circuit and a second precharge circuit. The first self-biasing circuit is coupled to a first data node to precharge the first data node in response to a first control signal. The first precharge circuit is coupled to the first data node to precharge the first data node in response to a second control signal. The second self-biasing circuit is coupled to a second data node in response the first control signal. The second precharge circuit is coupled to the second data node to precharge the second data node in response to the second control signal. Moreover, the second control signal is different from the first control signal.
In another embodiment, a non-volatile memory sense amplifier comprises a first self-bias circuit, a first precharge circuit, a second self-bias circuit, a second precharge circuit, and a comparator. The first self-bias circuit is coupled to precharge an array data node in response to a first control signal. The first precharge circuit coupled in concert with the first bias circuit to precharge the array data node in response to a second control signal. The second bias circuit is coupled to precharge a reference data node in response to the first control signal. The second precharge circuit is coupled in concert with the second bias circuit to precharge the reference data node in response to the second control signal. Moreover, the comparator is coupled to sense differences in current draw between the reference data node and the array data node.
In another embodiment, a Flash memory sense amplifier comprises, an array self-bias circuit, an array precharge circuit, an array limiting n-channel transistor, a reference self-bias circuit, a reference precharge circuit and a reference limiting n-channel transistor. The array self-bias circuit is coupled to source current to an array data node in response to a sense amplifier control signal. The array precharge circuit is used to aid the array self-bias circuit source current to the array data node in response to a precharge control signal. The array limiting n-channel transistor is coupled to the array self-bias circuit and the array precharge circuit to limit the amount of current sourced to the array data node. The reference self-bias circuit is coupled to source current to a reference data node in response to the sense amplifier control signal. The reference precharge circuit is used to aid the reference self-bias circuit source current to the reference data node in response to the precharge control signal. In addition, the reference limiting n-channel transistor is coupled to the reference self-bias circuit and the reference precharge circuit to limit the amount of current sourced to the reference data node.
In another embodiment, a Flash memory device comprises a sense amplifier, a memory array, a multiplexer circuit, a reference current draw circuit, an array data line and a matching capacitance data line. The sense amplifier comprises, a first self-bias circuit that is coupled to precharge an array data node, an array precharge circuit that is coupled to provide a current pulse in concert with the first bias circuit to precharge the array data node faster, a second bias circuit that is coupled to precharge a reference data node, a reference precharge circuit that is coupled to provide a current pulse in concert with the second bias circuit to precharge the reference data node faster, an equilibrate circuit that is coupled to equilibrate the array data node, and the reference data node and a comparator coupled to sense differences in current draw between the reference data node and the array data node. The memory array has a plurality of memory cells. The multiplexer circuit is coupled to the memory array to selectively couple the array data line and the reference data line to specific memory cells. The reference current draw circuit is coupled to the reference data node to provide a reference current draw. The array data line is coupled between the array data node and the memory array via the multiplexer circuit. The matching capacitance data line is coupled between the reference data node and the memory array via the multiplexer circuit. The array data line is precharged by the first self-bias circuit and the array precharge circuit and the matching capacitance data line is precharged by the second self-bias circuit and the reference precharge circuit.
In another embodiment, a method of precharging a data line with a sense amplifier is disclosed. The method comprising applying a first control signal to a self-bias circuit coupled to precharge the data line and applying a second control signal to a precharge circuit coupled to precharge the data line in concert with the self-bias circuit, wherein the second control signal is different from the first control signal.
In another embodiment, a method of precharging a data line with a sense amplifier is disclosed. The method comprising, activating a relatively small p-channel pull-up transistor in a diode configuration that has a source coupled to a voltage source and a drain selectively coupled to the data line and activating a n-channel pull-up transistor for a predetermined time period, the n-channel pull-up transistor having a drain selectively coupled to the voltage source and a source selectively coupled to the data line to aid the p-channel pull-up transistor precharge the data line.
In another embodiment, a method of operating a Flash memory sense amplifier is disclosed. The method comprising, initiating a read operation on a memory cell, activating an equilibrate circuit to equilibrate nodes within the sense amplifier, precharging a pair of global data lines with a pair of self -bias circuits, precharging the global data lines faster with an additional current pulse from a pair of n-channel pull-up transistors located in the sense amplifier and comparing a current draw of the memory cell coupled to one of the global data lines with a current draw of a reference cell.
In yet another embodiment, a method of operating a Flash memory is disclosed. The method comprising initiating a read operation of a memory cell in a memory array, enabling a sense amplifier with a sense amplifier control signal, activating an equilibrate circuit to equilibrate nodes within the sense amplifier, activating a first self-bias circuit within an array circuit of the sense amplifier to precharge an array data line, activating an array precharge circuit within the sense amplifier to provide a current pulse to the array data line to aid the array self-bias circuit precharge the array data line, activating a second self-bias circuit within a reference circuit of the sense amplifier to precharge a matching capacitance data line, activating a reference precharge circuit within the sense amplifier to provide a current pulse to the matching capacitance data line to aid the reference self-bias circuit precharge the matching capacitance data line, deactivating the equilibrate circuit and sensing a difference in current draw between the memory cell and a reference cell to determine a program state of the memory cell.